To define a new symbol, insert the symbol name and it's initial value and press 'Add'. The checkbox ' Make Default?' makes the current subdiagram the default diagram if none of the conditions for any subdiagram was met.Д¬onditional Disable symbols in the project properties dialog.Д¬onditional disable symbols can be defined in the project properties on the Conditional Disable Symbols page. If more than one condition is defined, a new drop-down list appears on the left which defines how the results of conditions are evaluated. The buttons ' +' and ' -' add or remove additional conditions. The next drop-down list after Symbol(s) defines the condition for the value. However, the symbol will not appear in the project automatically. A new symbol can be defined by manually writing the symbol name in the drop-down list. Opens the Configure Condition dialog box for the current subdiagram.ДЄll available symbols are listed in the drop-down list under Symbol(s). This dialog box appears for any of the following right-click menu options.ДЄdds a subdiagram after the current diagram.ДЄdds a subdiagram before the current diagram. The value of the symbol must be different (not equal) to the specified value.Д®ach subdiagram can have one or more conditions.Д¬onditions are defined in the Configure Condition dialog box. The value of the symbol must be equal to the specified value. The Diagram Disable structure supports two conditions: Available values depend on the connected FPGA target and can be accessed from the FPGA Target Properties dialog box. Symbols are available if the VI is placed under an FPGA target in the project.Дetermines the execution mode of the subdiagram within an FPGA VI.Д®xecutes in a Simulated I/O simulation environment.Д®xecutes in a Real I/O simulation environment.Д®xecutes in a Third-Party simulation environment.Дetermines the FPGA class. These symbols are defined by the LabVIEW FPGA module and cannot be changed. These symbols are only available for VIs inside projects.Дetermines the CPU on which the subdiagram executes. These symbols are defined by LabVIEW and cannot be changed.Дetermines if the subdiagram is executed in the Run-Time Engine.Дetermines on which platforms or targets the subdiagram executes.Дetermines the bitness of the platform to execute the subdiagram. If the FPGA module is installed, the additional symbols FPGA_EXECUTION_MODE, FPGA_TARGET_FAMILY and FPGA_TARGET_CLASS are made available.ДЄdditional symbols can be added via the project properties.Д®nvironment and project symbols are managed by LabVIEW and cannot be changed. If a VI is located inside a project, the additional symbols CPU and OS are available by default. LabVIEW always provides the environment symbols RUN_TIME_ENGINE, TARGET_TYPE and TARGET_BITNESS by default. Symbols are unique identifiers that have case-sensitive values of alpha-numeric characters and underscores ( +). The subdiagram to execute is determined based on conditions in the project that are evaluated at compile-time. The Conditional Disable Structure is a primitive structure that can have one or more subdiagrams (also known as 'Cases'), one of which is executed at runtime. Components of a Diagram Disable structure

Labview fpga simulation